A. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method applied to, for example, a drive circuit having a floating potential as a reference.
B. Description of the Related Art
Power devices such as insulated gate bipolar transistors (IGBT) or power metal-oxide-semiconductor field-effect transistors (MOSFET) are utilized in many fields, such as motor controlling inverters, plasma display panels (PDP), power supply applications for flat panel displays (FPD) such as liquid crystal panels, and inverters for household electrical appliances such as air conditioners and lighting.
To date, an electronic circuit configured by combining semiconductor devices such as a photocoupler and electronic parts such as a transformer has been used for the drive and control of these power devices. In recent years, however, high breakdown voltage ICs of breakdown voltage classes from 200V to 1,200V used in a range from household power supplies of 100V and 200V AC to industrial power supplies of 400V AC, and the like have been put to practical use, owing to the advance in large scale integration (LSI) technology.
There are a wide variety of high breakdown voltage ICs, encompassing gate driver ICs incorporating a high side gate driver and low side gate driver that control a power device, products incorporating overheat protection and overcurrent protection functions, and furthermore, single chip inverter ICs wherein a control circuit and power device are integrated on the same semiconductor substrate, and the like. The high breakdown voltage IC contributes greatly to a reduction in size and increase in efficiency of an overall inverter system owing to a reduction in the number of parts on a mounting board.
Generally, a high breakdown voltage IC is such that high side and low side drive logic devices are incorporated inside an IC. These logic devices are an n-type channel MOSFET and p-type channel MOSFET with a source-to-drain breakdown voltage of in the region of 20 to 30V, and are also used in a drive circuit.
Normally, as well as the n-type channel MOSFET and p-type channel MOSFET, a protection element such as a diode for electric static discharge (ESD) protection is connected in parallel to an input/output (I/O) terminal in the high voltage breakdown IC between a power supply terminal and ground terminal or between a high side power supply terminal and high side potential reference terminal.
Electrostatic destruction of a semiconductor device due to ESD refers to a destruction phenomenon whereby IC or LSI gate oxide film destruction or diffusion layer junction destruction, fusion of aluminum wiring, or the like, is caused by static electricity. When expressed as voltage, the static electricity often reaches a voltage of several hundred volts to several thousand volts, and when this kind of high voltage is applied to an input/output terminal of an IC or the like, an internal circuit, wiring, or the like of the IC may be destroyed.
As the n-type channel MOSFET and p-type channel MOSFET are of a push-pull configuration, there is rarely a problem of ESD surge destruction with regard to a driver circuit output terminal, or the like, in a high breakdown voltage IC. However, in the case of a high breakdown voltage IC incorporating a protection function such as abnormality detection, or the like, it is often the case that an n-type channel MOSFET with an open drain configuration, or the like, is used for an abnormal current detection output terminal in order to input a signal into an external personal computer, or the like, at a low voltage.
In the case of the open drain n-type channel MOSFET, as there is no body diode (built-in diode) path to the power supply side in a p-type channel MOSFET, it is often the case that the n-type channel MOSFET itself causes junction destruction due to ESD surge, power supply noise, or the like. Because of this, it is necessary to provide an ESD protection diode, or the like, over a large area in the abnormal current detection output terminal, or the like, and there is a cost-related problem in that chip size increases because of an increase in protection element area in a sophisticated IC. Also, an n-type channel MOSFET on a high side well used in a power IC, particularly in a high breakdown voltage IC incorporating a high side triple well structure, is such that ESD resistance is liable to decrease, and there is a problem in that an ESD protection diode with a large area is necessary in order to prevent this decrease.
FIGS. 10A and 10B are diagrams illustrating a heretofore known semiconductor device 500, wherein FIG. 10A is a main portion sectional view, and FIG. 10B is an enlargement of a B portion of FIG. 10A showing depletion layer 80 inside second n-type offset layer 67. The semiconductor device is a high side n-type channel MOSFET 501 of a triple well structure.
High side n-type channel MOSFET 501 has a high side n-type channel MOSFET of a triple well structure (configured of first p-type well layer 53, and n-type well layer 52 and second p-type well layer 60 shown in the drawings). FIGS. 10A and 10B are main portion sectional views of the high side n-type channel MOSFET with the triple well structure.
N-type channel MOSFET 501 configuring semiconductor device 500 includes first p-type well layer 53 and n-type well layer 52 disposed in a surface layer of p-type semiconductor substrate 51, and second p-type well layer 60 formed by diffusion in a surface layer of n-type well layer 52. First p-type well layer 53 includes in a surface layer contact layer 75 for applying a predetermined potential to p-type semiconductor substrate 51.
Also, n-type channel MOSFET 501 includes first n-type offset layer 66 and second n-type offset layer 67 selectively formed by diffusion to be distanced from each other in a surface layer of second p-type well layer 60, n-type drain layer 72 formed by diffusion in a surface layer of second n-type offset layer 67, and n-type source layer 73 formed by diffusion in a surface layer of first n-type offset layer 66. Also, n-type channel MOSFET 501 includes p-type base layer 71, in contact with first n-type offset layer 67 and connected to second p-type well layer 60, and p-type contact layer 74 in contact with p-type base layer 71 and n-type source layer 73.
Also, a LOCOS oxide film (hereafter abbreviated to LOCOS 68) is provided on second n-type offset layer 67, second p-type well layer 60, n-type well layer 52, and p-type semiconductor substrate 51.
Also, thick gate oxide film 69 is provided on p-type well layer 60 sandwiched by first n-type offset layer 66 and second n-type offset layer 67, and gate electrode 70 is provided extending from thick gate oxide film 69 to LOCOS 68.
Also, n-type channel MOSFET 501 includes a drain electrode (not shown) connected to n-type drain layer 72 and a source electrode (not shown) connected to n-type source layer 73 and p-type contact layer 74.
Second p-type well layer 60 disposed below gate electrode 70 forms a back gate region.
As shown in FIGS. 11A and 11B, to be described hereafter, n-type channel MOSFET 501 is such that the surface of second p-type well layer 60 formed on n-type well layer 52 below LOCOS 68 and below thick gate oxide film 69 is locally of a low concentration. This is because of the out-diffusion (drawing out) effect of boron impurities when carrying out a pyro-oxidation step.
However, as LOCOS 68 is not formed on the surface of second p-type well layer 60 below n-type drain layer 72, there is no out-diffusion effect. Because of this, the boron concentration is high compared with that below LOCOS 68 and thick gate oxide film 69.
FIGS. 11A and 11B are diagrams showing the relationship between impurity concentration and depth, wherein FIG. 11A is a diagram illustrating second p-type well layer 60, and FIG. 11B is a diagram illustrating second n-type offset layer 67. In FIG. 11A, the boron concentration below LOCOS 68 decreases farther than that below n-type drain layer 72 owing to out-diffusion (drawing out). In other words, the boron concentration of region 61 below n-type drain layer 72 is higher than the boron concentration of region 62 below LOCOS 68. Meanwhile, as boron impurities are absorbed by LOCOS 68 on the surface, the boron concentration of second p-type well layer 60 in a junction place Q with n-type well layer 52 is the same in both regions.
Because of this, second n-type offset layer 67 formed as a drain drift region of n-type channel MOSFET 501 is such that a thickness T1 below LOCOS 68 is large, while a thickness To below n-type drain layer 72 is small, as shown in FIG. 11B. As a result of this, the thickness To of second n-type offset layer 67 below n-type drain layer 72 is small at less than 1 μm in the heretofore known structure. When an ESD surge is applied to the drain, second n-type offset layer 67 is depleted from a junction portion between second p-type well layer 60 and second n-type offset layer 67. The depletion process is such that, as the thickness To of second n-type offset layer 67 below n-type drain layer 72 is small at less than 1 μm, depletion layer 80 spreads at a low reverse voltage, and depletion layer 80 reaches n-type drain layer 72, causing a localized electrical field concentration (the mark × in FIGS. 10A and 10B). As a result of this, when an ESD surge is applied to the drain, an electrical field concentration is caused below n-type drain layer 72, leading to junction destruction at a low ESD applied voltage of in the region of, for example, 1,700V.
FIG. 12 is a diagram showing the relationship between the drain voltage and drain current when an ESD surge is input into the drain of the n-type channel MOSFET 501 with the heretofore known high side structure. The diagram shows the appearance of a snapback waveform after avalanche breakdown.
As second n-type offset layer 67 below n-type drain layer 72 is shallow in n-type channel MOSFET 501 of FIGS. 10A and 10B, an electrical field concentrates in the junction portion of second n-type offset layer 67 and second p-type well layer 60, and the breakdown voltage decreases. Furthermore, as second n-type offset layer 67 below n-type drain layer 72 is completely depleted, second n-type offset layer 67 becomes a negative resistor after snapback, and localized current concentration occurs, as shown in FIG. 12. Because of this, the ESD resistance decreases.
To date, in order to increase the ESD resistance of a MOSFET used as a driver element of a power IC or the like, it has been important to alleviate an electrical field at the drain end, thereby avoiding a localized current concentration, when an ESD surge is input into the drain. In order to do this, an additional buffer layer is introduced into the drain so that the depletion layer does not reach the n-type drain layer, as in “A New Adaptive Resurf Concept for 20V LDMOS Without Breakdown Voltage Degradation at High Current”, ISPSD, 1998 (Kyoto) pages 65 to 68.
As a way of doing this, there is an employment of an adaptive resurf (buffer) structure that suppresses a change to negative resistance after avalanche, an adopting of a thyristor structure by adding a p+ anode layer on the drain side, as in JP-A-2002-94063, and the like.
In “A New Adaptive Resurf Concept for 20V LDMOS Without Breakdown Voltage Degradation at High Current”, ISPSD, 1998 (Kyoto) pages 65 to 68, by introducing an additional buffer layer in the drain of an LDMOS so that the depletion layer does not reach the n-type drain layer when there is reverse bias, the buffer layer portion is caused to function as a resistance component. Because of this, a localized current concentration occurring after avalanche is suppressed by the resistance component, and it is possible to cause current to flow evenly through the whole of the cell, because of which the ESD resistance per unit element area increases.
Also, in JP-A-2002-94063, avalanche breakdown occurs in an end portion on the LOCOS oxide film side of the drain layer, because of which electrons and holes are generated. The electrons generated flow into the drain layer, while the holes flow into a back gate layer. At this time, a parasitic bipolar transistor formed of the n-type drain layer, p-type base (back gate) layer, and n-type source layer changes to an on-state. By the parasitic bipolar transistor changing to an on-state, the voltage between the source layer and drain layer is clamped at a low voltage, and the ESD surge voltage is suppressed.
However, when a localized current concentration occurs in the end portion of the drain layer, thermal runaway occurs in this region. Because of this, sufficient ESD resistance is not obtained, and junction destruction may occur in the drain layer. In order to prevent this destruction, holes are implanted from the p+ anode layer after the parasitic bipolar transistor changes to an on-state by adding a p+ anode layer on the drain side, and there is a shift to a thyristor action, reducing the hold voltage and suppressing current concentration.
However, in “A New Adaptive Resurf Concept for 20V LDMOS Without Breakdown Voltage Degradation at High Current”, ISPSD, 1998 (Kyoto) pages 65 to 68 and in JP-A-2002-94063, it is necessary to add a buffer layer on the drain side, or necessary to add a deep p+ anode layer, in order to increase the ESD resistance of the LDMOS. Because of this, the number of processes increases owing to patterning and ion implantation steps using a dedicated mask, leading to an increase in cost.
Also, when attempting to apply the previously described measures to the high side region of a triple well structure, it is necessary to configure a high side n-type channel MOSFET by forming a well layer, which forms a back gate region on an n-type well layer forming a high side high potential layer, and an n-type offset layer that forms a source-to-drain layer. However, when forming the adaptive resurf (buffer) layer more deeply than the drain side n-type offset layer, a problem occurs in that punch-through breakdown voltage between the adaptive resurf (buffer) layer and high potential n-type well layer decreases. Also, with regard to the addition of a p+ anode layer on the drain side, application is difficult as it leads to a decrease in punch-through or junction breakdown voltage occurring between the p-type well layer on the high side n-type well layer and the p+ anode layer disposed on the n-type offset layer. In either case, no description or suggestion of improving the ESD resistance in a high side logic device with a triple well structure is found in “A New Adaptive Resurf Concept for 20V LDMOS Without Breakdown Voltage Degradation at High Current”, ISPSD, 1998 (Kyoto) pages 65 to 68 or in JP-A-2002-94063.
Next, a description will be given of JP-A-11-111855. In JP-A-11-111855, a photomask having a mask pattern with widely differing ion implantation areas is used. It is described that, by an opening portion with no photoresist being formed in a region that is to form a high concentration p-type well region, and an opening portion in which photoresist remains in slit form being formed in a region that is to form a low concentration p-type well region, using the photomask, and an ion implantation being carried out, a condensing of steps and a reduction in chip cost are achieved.
However, the photoresist opening portion for forming the high concentration p-type well region and the photoresist opening portion for forming the low concentration p-type well region are separated into two regions, and each is formed as a separate well region. Because of this, the slit form resist opening portion is not provided in one portion in the same p-type well region.
Also, in JP-T-2012-519371 (the term “JP-T” as used herein means a published Japanese translation of a PCT patent application), a high breakdown voltage semiconductor device includes an n− type region, provided on a p− type silicon substrate and enclosed by a p− type well region, and a drain n+ type region connected to a drain electrode. The high breakdown voltage semiconductor device includes a p-type base region, provided distanced from the drain n+ type region and enclosing the drain n+ type region, and a source n+ type region formed inside the p-type base region. Also, a p− type region penetrating the n− type region and reaching the silicon substrate is provided. The n− type region is divided in two by the p− type region. One n− type region includes the drain n+ type region. The other n− type region has a floating potential. It is described that the high breakdown voltage semiconductor device is adopted as a high breakdown voltage transistor with high switching response speed and a drive circuit that suppresses power loss and malfunction.